1. Field of the Invention
The present invention relates to a fault tolerant system and controller, access control method, and control program used in the fault tolerant system and, more particularly, to an access control from a processor to an IO device for realizing a fault tolerant configuration in a computer system.
2. Description of the Related Art
Conventionally known is a fault tolerance computer system (hereinafter, referred to as “fault tolerance system”) in which all components, such as a CPU (Central Processing Unit), memory, PCI (Peripheral Component Interconnect), disk, power source, and the like, that constitute a computer hardware are multiplexed (for example, duplicated or triplicated). In such a computer system, even if a failure occurs in any of components, the system can continue operating without interruption.
In the fault tolerant system, a multiplexed plurality of CPUs (processors) executes the same operation at the same timing while constantly establishing synchronization between them (which is referred to as “lock-step synchronization”). Even if a failure occurs in one of the plurality of CPUs that execute the same operation in lock-step synchronization, other CPUs continue normal operation. That is, if any failure occurs, the fault tolerant system can continue operating without adversely affecting the operation of software such as an operating system or application software executed by the CPU.
As related arts concerning such a fault tolerant system, U.S. patent application publication No. 2002/0152418 A1 discloses an apparatus and method for executing instructions in lock-step synchronization, U.S. patent application publication No. 2002/0152419 A1 discloses an apparatus and method for accessing a mass storage device in a fault-tolerant server, U.S. Pat. No. 5,953,742 discloses a technique of making a memory copy between a plurality of processing sets each including a processor that operates in lock-step synchronization to establish high-speed resynchronization, and U.S. Pat. No. 5,751,932 discloses a configuration including routers belonging to two systems between which CPUs process the same instruction in lock-step synchronization, the routers routing packets to not only the CPU and an IO device of its own system but also those in other system.
It is required for the above fault tolerant system to process accesses issued from a plurality of CPUs as individual accesses when the CPUs are in an asynchronous state and to process accesses issued from the CPUs as common accesses when the CPUs are in a lock-step synchronous state. The above-related arts, however, have not been made in view of the access processing performed in accordance with synchronous/asynchronous state between the CPUs.